pool_machine.h

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/*
 * Copyright (c) 2015-2020 Seagate Technology LLC and/or its Affiliates
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 * For any questions about this software or licensing,
 * please email opensource@seagate.com or cortx-questions@seagate.com.
 *
 */


#pragma once

#ifndef __MOTR_POOL_MACHINE_H__
#define __MOTR_POOL_MACHINE_H__

#include "format/format.h" /* m0_be_clink */
#include "format/format_xc.h"
#include "lib/tlist.h"
#include "lib/tlist_xc.h"
#include "lib/rwlock.h"    /* m0_rwlock */
#include "conf/obj.h"      /* m0_conf_pver_kind */

/* import */
struct m0_sm_group;
struct m0_dtm;
struct m0_dtx;
struct m0_be_tx_credit;
struct m0_poolnode;
struct m0_pooldev;
struct m0_pool_spare_usage;
struct m0_pools_common;
struct m0_poolmach_event;
struct m0_poolmach_event_link;
struct m0_confc;
struct m0_conf_pver;
struct m0_motr;

enum m0_pool_nd_state {
        M0_PNDS_UNKNOWN,

        M0_PNDS_ONLINE,

        M0_PNDS_FAILED,

        M0_PNDS_OFFLINE,

        M0_PNDS_SNS_REPAIRING,

        M0_PNDS_SNS_REPAIRED,

        M0_PNDS_SNS_REBALANCING,

        M0_PNDS_NR
} M0_XCA_ENUM;

enum {
        /* Unused spare slot has this device index */
        POOL_PM_SPARE_SLOT_UNUSED = 0xFFFFFFFF
};

struct m0_poolmach_state {
        uint32_t                    pst_nr_nodes;

        struct m0_poolnode         *pst_nodes_array;

        uint32_t                    pst_nr_devices;

        struct m0_pooldev          *pst_devices_array;

        uint32_t                    pst_max_node_failures;

        uint32_t                    pst_nr_spares;

        uint32_t                    pst_max_device_failures;

        uint32_t                    pst_nr_failures;

        struct m0_pool_spare_usage *pst_spare_usage_array;

        bool                        pst_su_initialised;

        struct m0_tl                pst_events_list;

        struct m0_tl                pst_event_queue;

        struct m0_be_clink          pst_conf_exp;
        struct m0_be_clink          pst_conf_ready;
};

struct m0_poolmach {
        struct m0_poolmach_state *pm_state;

        struct m0_pool_version    *pm_pver;

        bool                       pm_is_initialised;

        struct m0_rwlock           pm_lock;
};

enum m0_poolmach_event_owner_type {
        M0_POOL_NODE,
        M0_POOL_DEVICE
};

struct m0_poolmach_event {
        uint32_t              pe_type M0_XCA_FENUM(
                m0_poolmach_event_owner_type);

        uint32_t              pe_index;

        enum m0_pool_nd_state pe_state;
};

struct m0_poolmach_event_link {
        struct m0_poolmach_event    pel_event;

        struct m0_tlink             pel_linkage;

        uint64_t                    pel_magic;
};

M0_INTERNAL uint32_t m0_poolmach_equeue_length(struct m0_poolmach *pm);

M0_INTERNAL int m0_poolmach_init(struct m0_poolmach *pm,
                                 struct m0_pool_version *pver,
                                 uint32_t            nr_nodes,
                                 uint32_t            nr_devices,
                                 uint32_t            nr_spare,
                                 uint32_t            max_node_failures,
                                 uint32_t            max_device_failures);

M0_INTERNAL int m0_poolmach_init_by_conf(struct m0_poolmach *pm,
                                         struct m0_conf_pver *pver);

M0_INTERNAL void m0_poolmach_fini(struct m0_poolmach *pm);

M0_INTERNAL void m0_poolmach_event_queue_apply(struct m0_poolmach *pmach);

M0_INTERNAL void m0_poolmach_failvec_apply(struct m0_poolmach *pmach,
                                           const struct m0_ha_nvec *nvec);

M0_INTERNAL int m0_poolmach_state_transit(struct m0_poolmach *pm,
                                          const struct m0_poolmach_event *event);
M0_INTERNAL void m0_poolmach_state_last_cancel(struct m0_poolmach *pm);

M0_INTERNAL int m0_poolmach_device_state(struct m0_poolmach *pm,
                                         uint32_t device_index,
                                         enum m0_pool_nd_state *state_out);

M0_INTERNAL int m0_poolmach_node_state(struct m0_poolmach *pm,
                                       uint32_t node_index,
                                       enum m0_pool_nd_state *state_out);

M0_INTERNAL int m0_poolmach_device_node_return(struct m0_poolmach *pm,
                                               uint32_t device_index,
                                               struct m0_poolnode **node_out);

M0_INTERNAL bool
m0_poolmach_device_is_in_spare_usage_array(struct m0_poolmach *pm,
                                           uint32_t device_index);

M0_INTERNAL int m0_poolmach_sns_repair_spare_query(struct m0_poolmach *pm,
                                                   uint32_t device_index,
                                                   uint32_t *spare_slot_out);

M0_INTERNAL bool
m0_poolmach_sns_repair_spare_contains_data(struct m0_poolmach *pm,
                                           uint32_t spare_slot,
                                           bool check_state);

M0_INTERNAL int m0_poolmach_sns_rebalance_spare_query(struct m0_poolmach *pm,
                                                      uint32_t device_index,
                                                      uint32_t *spare_slot_out);

M0_INTERNAL void m0_poolmach_event_dump(const struct m0_poolmach_event *e);
M0_INTERNAL void m0_poolmach_event_list_dump(struct m0_poolmach *pm);
M0_INTERNAL void m0_poolmach_event_list_dump_locked(struct m0_poolmach *pm);
M0_INTERNAL void m0_poolmach_device_state_dump(struct m0_poolmach *pm);
M0_INTERNAL uint64_t m0_poolmach_nr_dev_failures(struct m0_poolmach *pm);

M0_INTERNAL int m0_poolmach_fid_to_idx(struct m0_poolmach *pm,
                                       struct m0_fid *fid, uint32_t *idx);

M0_TL_DESCR_DECLARE(poolmach_events, M0_EXTERN);
M0_TL_DECLARE(poolmach_events, M0_INTERNAL, struct m0_poolmach_event_link);

M0_INTERNAL void m0_poolmach_gob2cob(struct m0_poolmach *pm,
                                     const struct m0_fid *gfid,
                                     uint32_t idx,
                                     struct m0_fid *cob_fid_out);

M0_INTERNAL int m0_poolmach_spare_build(struct m0_poolmach *mach,
                                        struct m0_pool *pool,
                                        enum m0_conf_pver_kind kind);
#endif /* __MOTR_POOL_PVER_MACHINE_H__ */

/*
 *  Local variables:
 *  c-indentation-style: "K&R"
 *  c-basic-offset: 8
 *  tab-width: 8
 *  fill-column: 80
 *  scroll-step: 1
 *  End:
 */