Motr  M0
test_pm.c
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1 /* -*- C -*- */
2 /*
3  * Copyright (c) 2012-2020 Seagate Technology LLC and/or its Affiliates
4  *
5  * Licensed under the Apache License, Version 2.0 (the "License");
6  * you may not use this file except in compliance with the License.
7  * You may obtain a copy of the License at
8  *
9  * http://www.apache.org/licenses/LICENSE-2.0
10  *
11  * Unless required by applicable law or agreed to in writing, software
12  * distributed under the License is distributed on an "AS IS" BASIS,
13  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14  * See the License for the specific language governing permissions and
15  * limitations under the License.
16  *
17  * For any questions about this software or licensing,
18  * please email opensource@seagate.com or cortx-questions@seagate.com.
19  *
20  */
21 
22 
23 #include "ut/ut.h"
24 #include "lib/memory.h"
25 #include "lib/misc.h"
26 #include "pool/pool.h"
27 #include "cob/cob.h"
28 #include "ut/be.h"
29 #include "be/ut/helper.h"
30 #include "ha/note.h" /* m0_ha_nvec */
31 
32 #undef M0_TRACE_SUBSYSTEM
33 #define M0_TRACE_SUBSYSTEM M0_TRACE_SUBSYS_POOL
34 #include "lib/trace.h" /* M0_LOG */
35 #include "lib/finject.h" /* m0_fi_enable_off_n_on_m() m0_fi_disable() */
36 
37 enum {
43 };
44 
45 static struct m0_fid M0_POOL_ID = M0_FID_TINIT('o', 1, 23);
46 static struct m0_fid M0_PVER_ID = M0_FID_TINIT('v', 1, 24);
47 static struct m0_pool pool;
48 static struct m0_pool_version pver;
49 
50 static int pool_pver_init(uint32_t N, uint32_t K, uint32_t S)
51 {
52  int rc;
53 
54  M0_SET0(&pool);
56  M0_SET0(&pver);
60 
61  return rc;
62 }
63 
64 static void pool_pver_fini(void)
65 {
66  m0_fi_enable_once("m0_poolmach_fini", "poolmach_init_by_conf_skipped");
69 }
70 
71 static void pm_test_init_fini(void)
72 {
73  int rc;
74 
77  M0_UT_ASSERT(rc == 0);
79 }
80 
81 static void pm_test_transit(void)
82 {
83  struct m0_poolmach *pm;
84  enum m0_pool_nd_state state;
85  int rc;
86  struct m0_poolmach_event events[4];
87  struct m0_poolmach_event e_invalid;
88  struct m0_poolmach_event e_valid;
89  struct m0_ha_nvec nvec;
90 
91  M0_SET0(&nvec);
94  M0_UT_ASSERT(rc == 0);
95  pm = &pver.pv_mach;
96  m0_poolmach_failvec_apply(pm, &nvec);
97 
98  events[0].pe_type = M0_POOL_DEVICE;
99  events[0].pe_index = 1;
100  events[0].pe_state = M0_PNDS_FAILED;
101  rc = m0_poolmach_state_transit(pm, &events[0]);
102  M0_UT_ASSERT(rc == 0);
103 
104  events[1].pe_type = M0_POOL_DEVICE;
105  events[1].pe_index = 3;
106  events[1].pe_state = M0_PNDS_OFFLINE;
107  rc = m0_poolmach_state_transit(pm, &events[1]);
108  M0_UT_ASSERT(rc == 0);
109 
110  events[2].pe_type = M0_POOL_DEVICE;
111  events[2].pe_index = 3;
112  events[2].pe_state = M0_PNDS_ONLINE;
113  rc = m0_poolmach_state_transit(pm, &events[2]);
114  M0_UT_ASSERT(rc == 0);
115 
116  events[3].pe_type = M0_POOL_NODE;
117  events[3].pe_index = 0;
118  events[3].pe_state = M0_PNDS_OFFLINE;
119  rc = m0_poolmach_state_transit(pm, &events[3]);
120  M0_UT_ASSERT(rc == 0);
121 
122  /* invalid event. case 1: invalid type*/
123  e_invalid.pe_type = M0_POOL_NODE + 5;
124  e_invalid.pe_index = 0;
125  e_invalid.pe_state = M0_PNDS_OFFLINE;
126  rc = m0_poolmach_state_transit(pm, &e_invalid);
127  M0_UT_ASSERT(rc == -EINVAL);
128 
129  /* invalid event. case 2: invalid index */
130  e_invalid.pe_type = M0_POOL_NODE;
131  e_invalid.pe_index = 100;
132  e_invalid.pe_state = M0_PNDS_OFFLINE;
133  rc = m0_poolmach_state_transit(pm, &e_invalid);
134  M0_UT_ASSERT(rc == -EINVAL);
135 
136  /* invalid event. case 3: invalid state */
137  e_invalid.pe_type = M0_POOL_NODE;
138  e_invalid.pe_index = 0;
139  e_invalid.pe_state = M0_PNDS_SNS_REBALANCING + 1;
140  rc = m0_poolmach_state_transit(pm, &e_invalid);
141  M0_UT_ASSERT(rc == -EINVAL);
142 
143  /* invalid event. case 4: invalid state */
144  e_invalid.pe_type = M0_POOL_DEVICE;
145  e_invalid.pe_index = 0;
146  e_invalid.pe_state = M0_PNDS_NR;
147  rc = m0_poolmach_state_transit(pm, &e_invalid);
148  M0_UT_ASSERT(rc == -EINVAL);
149 
150  /* Test transition from M0_PNDS_OFFLINE to M0_PNDS_FAILED. */
151  rc = m0_poolmach_device_state(pm, 0, &state);
152  M0_UT_ASSERT(rc == 0 && state == M0_PNDS_UNKNOWN);
153 
154  e_valid.pe_type = M0_POOL_DEVICE;
155  e_valid.pe_index = 0;
156  e_valid.pe_state = M0_PNDS_OFFLINE;
157  rc = m0_poolmach_state_transit(pm, &e_valid);
158  M0_UT_ASSERT(rc == 0);
159  rc = m0_poolmach_device_state(pm, 0, &state);
160  M0_UT_ASSERT(rc == 0 && state == M0_PNDS_OFFLINE);
161 
162  e_valid.pe_type = M0_POOL_DEVICE;
163  e_valid.pe_index = 0;
164  e_valid.pe_state = M0_PNDS_FAILED;
165  rc = m0_poolmach_state_transit(pm, &e_valid);
166  M0_UT_ASSERT(rc == 0);
167  rc = m0_poolmach_device_state(pm, 0, &state);
168  M0_UT_ASSERT(rc == 0 && state == M0_PNDS_FAILED);
169 
170  m0_fi_enable_off_n_on_m("m0_pooldev_clink_del",
171  "do_nothing_for_poolmach-ut", 0,
173  /* Destroy poolmach persistent storage. We will have some different
174  * poolmach parameters in next test case.
175  */
176  m0_fi_disable("m0_pooldev_clink_del", "do_nothing_for_poolmach-ut");
177  /* finally */
178  pool_pver_fini();
179 }
180 
181 static void pm_test_spare_slot(void)
182 {
183  struct m0_poolmach *pm;
184  struct m0_ha_nvec nvec;
185  int rc = 0;
186  struct m0_poolmach_event event;
187  enum m0_pool_nd_state state_out;
188  enum m0_pool_nd_state target_state;
189  enum m0_pool_nd_state state;
190  uint32_t spare_slot;
191 
192  rc = pool_pver_init(6, 2, 2);
193  M0_UT_ASSERT(rc == 0);
194  pm = &pver.pv_mach;
195 
196  M0_SET0(&nvec);
197  m0_poolmach_failvec_apply(pm, &nvec);
198  event.pe_type = M0_POOL_DEVICE;
199  event.pe_index = 1;
200 
201 
202  /* ONLINE */
203  target_state = M0_PNDS_ONLINE;
204  event.pe_state = target_state;
205  rc = m0_poolmach_state_transit(pm, &event);
206  M0_UT_ASSERT(rc == 0);
207  rc = m0_poolmach_device_state(pm, 1, &state_out);
208  M0_UT_ASSERT(rc == 0);
209  M0_UT_ASSERT(state_out == target_state);
210  /* FAILED */
211  target_state = M0_PNDS_FAILED;
212  event.pe_state = target_state;
213  rc = m0_poolmach_state_transit(pm, &event);
214  M0_UT_ASSERT(rc == 0);
215  rc = m0_poolmach_device_state(pm, 1, &state_out);
216  M0_UT_ASSERT(rc == 0);
217  M0_UT_ASSERT(state_out == target_state);
218 
220  &state_out);
221  M0_UT_ASSERT(rc == 0);
223  &state_out);
224  M0_UT_ASSERT(rc == -EINVAL);
225  rc = m0_poolmach_device_state(pm, 100, &state_out);
226  M0_UT_ASSERT(rc == -EINVAL);
227 
228  for (state = M0_PNDS_ONLINE; state < M0_PNDS_NR; state++) {
229  if (state == M0_PNDS_SNS_REPAIRING || state == M0_PNDS_FAILED)
230  continue;
231  /*
232  * transition to other state other than the above two states is
233  * invalid
234  */
235  event.pe_state = state;
236  rc = m0_poolmach_state_transit(pm, &event);
237  M0_UT_ASSERT(rc == -EINVAL);
238  }
239 
240  rc = m0_poolmach_device_state(pm, 1, &state_out);
241  M0_UT_ASSERT(rc == 0);
242  M0_UT_ASSERT(state_out == target_state);
243 
244 
245  /* transit to SNS_REPAIRING */
246  target_state = M0_PNDS_SNS_REPAIRING;
247  event.pe_state = target_state;
248  rc = m0_poolmach_state_transit(pm, &event);
249  M0_UT_ASSERT(rc == 0);
250  rc = m0_poolmach_device_state(pm, 1, &state_out);
251  M0_UT_ASSERT(rc == 0);
252  M0_UT_ASSERT(state_out == target_state);
253  /* the first spare slot is used by device 1 */
254  rc = m0_poolmach_sns_repair_spare_query(pm, 1, &spare_slot);
255  M0_UT_ASSERT(rc == 0);
256  M0_UT_ASSERT(spare_slot == 0);
257  /* no spare slot is used by device 2 */
258  rc = m0_poolmach_sns_repair_spare_query(pm, 2, &spare_slot);
259  M0_UT_ASSERT(rc == -ENOENT);
260  for (state = M0_PNDS_ONLINE; state < M0_PNDS_NR; state++) {
261  if (state == M0_PNDS_SNS_REPAIRED ||
262  state == M0_PNDS_FAILED ||
263  state == M0_PNDS_SNS_REPAIRING)
264  continue;
265  /* transit to other state other than the above one is invalid */
266  event.pe_state = state;
267  rc = m0_poolmach_state_transit(pm, &event);
268  M0_UT_ASSERT(rc == -EINVAL);
269  }
270 
271 
272  /* transit to SNS_REPAIRED */
273  target_state = M0_PNDS_SNS_REPAIRED;
274  event.pe_state = target_state;
275  rc = m0_poolmach_state_transit(pm, &event);
276  M0_UT_ASSERT(rc == 0);
277  rc = m0_poolmach_device_state(pm, 1, &state_out);
278  M0_UT_ASSERT(rc == 0);
279  M0_UT_ASSERT(state_out == target_state);
280  /* the first spare slot is used by device 1 */
281  rc = m0_poolmach_sns_repair_spare_query(pm, 1, &spare_slot);
282  M0_UT_ASSERT(rc == 0);
283  M0_UT_ASSERT(spare_slot == 0);
284  /* no spare slot is used by device 2 */
285  rc = m0_poolmach_sns_repair_spare_query(pm, 2, &spare_slot);
286  M0_UT_ASSERT(rc == -ENOENT);
287  for (state = M0_PNDS_ONLINE; state < M0_PNDS_NR; state++) {
288  if (state == M0_PNDS_SNS_REBALANCING ||
289  state == M0_PNDS_SNS_REPAIRED)
290  continue;
291  /* transit to other state other than the above one is invalid */
292  event.pe_state = state;
293  rc = m0_poolmach_state_transit(pm, &event);
294  M0_UT_ASSERT(rc == -EINVAL);
295  }
296 
297 
298  /* transit to SNS_REBALANCING */
299  target_state = M0_PNDS_SNS_REBALANCING;
300  event.pe_state = target_state;
301  rc = m0_poolmach_state_transit(pm, &event);
302  M0_UT_ASSERT(rc == 0);
303  rc = m0_poolmach_device_state(pm, 1, &state_out);
304  M0_UT_ASSERT(rc == 0);
305  M0_UT_ASSERT(state_out == target_state);
306  /* the first spare slot is used by device 1 */
307  rc = m0_poolmach_sns_rebalance_spare_query(pm, 1, &spare_slot);
308  M0_UT_ASSERT(rc == 0);
309  M0_UT_ASSERT(spare_slot == 0);
310  for (state = M0_PNDS_ONLINE; state < M0_PNDS_NR; state++) {
311  if (state == M0_PNDS_ONLINE ||
312  state == M0_PNDS_SNS_REBALANCING ||
313  state == M0_PNDS_SNS_REPAIRED ||
314  state == M0_PNDS_FAILED)
315  continue;
316  /* transit to other state other than the above one is invalid */
317  event.pe_state = state;
318  rc = m0_poolmach_state_transit(pm, &event);
319  M0_UT_ASSERT(rc == -EINVAL);
320  }
321 
322  /* transit to ONLINE */
323  target_state = M0_PNDS_ONLINE;
324  event.pe_state = target_state;
325  rc = m0_poolmach_state_transit(pm, &event);
326  M0_UT_ASSERT(rc == 0);
327  rc = m0_poolmach_device_state(pm, 1, &state_out);
328  M0_UT_ASSERT(rc == 0);
329  M0_UT_ASSERT(state_out == target_state);
330  /* the first spare slot is not used any more */
331  rc = m0_poolmach_sns_repair_spare_query(pm, 1, &spare_slot);
332  M0_UT_ASSERT(rc == -ENOENT);
333 
334  m0_fi_enable_off_n_on_m("m0_pooldev_clink_del",
335  "do_nothing_for_poolmach-ut", 0,
337  /* Destroy poolmach persistent storage. We will have some different
338  * poolmach parameters in next test case.
339  */
340  m0_fi_disable("m0_pooldev_clink_del", "do_nothing_for_poolmach-ut");
341  /* finally */
342  pool_pver_fini();
343 }
344 
345 static void pm_test_multi_fail(void)
346 {
347  struct m0_poolmach *pm;
348  struct m0_poolmach_event event;
349  struct m0_ha_nvec nvec;
350  enum m0_pool_nd_state state_out;
351  enum m0_pool_nd_state target_state;
352  uint32_t spare_slot;
353  int rc;
354 
355  rc = pool_pver_init(4, 3, 3);
356  M0_UT_ASSERT(rc == 0);
357  pm = &pver.pv_mach;
358  M0_SET0(&nvec);
359  m0_poolmach_failvec_apply(pm, &nvec);
360 
361  event.pe_type = M0_POOL_DEVICE;
362 
363  /* device 1 ONLINE */
364  event.pe_index = 1;
365  target_state = M0_PNDS_ONLINE;
366  event.pe_state = target_state;
367  rc = m0_poolmach_state_transit(pm, &event);
368  M0_UT_ASSERT(rc == 0);
369  rc = m0_poolmach_device_state(pm, 1, &state_out);
370  M0_UT_ASSERT(rc == 0);
371  M0_UT_ASSERT(state_out == target_state);
372 
373  /* device 1 FAILED */
374  event.pe_index = 1;
375  target_state = M0_PNDS_FAILED;
376  event.pe_state = target_state;
377  rc = m0_poolmach_state_transit(pm, &event);
378  M0_UT_ASSERT(rc == 0);
379  rc = m0_poolmach_device_state(pm, 1, &state_out);
380  M0_UT_ASSERT(rc == 0);
381  M0_UT_ASSERT(state_out == target_state);
382 
383  /* device 2 ONLINE */
384  event.pe_index = 2;
385  target_state = M0_PNDS_ONLINE;
386  event.pe_state = target_state;
387  rc = m0_poolmach_state_transit(pm, &event);
388  M0_UT_ASSERT(rc == 0);
389  rc = m0_poolmach_device_state(pm, 2, &state_out);
390  M0_UT_ASSERT(rc == 0);
391  M0_UT_ASSERT(state_out == target_state);
392 
393  /* device 2 FAILED */
394  event.pe_index = 2;
395  target_state = M0_PNDS_FAILED;
396  event.pe_state = target_state;
397  rc = m0_poolmach_state_transit(pm, &event);
398  M0_UT_ASSERT(rc == 0);
399  rc = m0_poolmach_device_state(pm, 2, &state_out);
400  M0_UT_ASSERT(rc == 0);
401  M0_UT_ASSERT(state_out == target_state);
402 
403  /* transit device 1 to SNS_REPAIRING */
404  event.pe_index = 1;
405  target_state = M0_PNDS_SNS_REPAIRING;
406  event.pe_state = target_state;
407  rc = m0_poolmach_state_transit(pm, &event);
408  M0_UT_ASSERT(rc == 0);
409  /* the first spare slot is used by device 1 */
410  rc = m0_poolmach_sns_repair_spare_query(pm, 1, &spare_slot);
411  M0_UT_ASSERT(rc == 0);
412  M0_UT_ASSERT(spare_slot == 0);
413 
414  /* transit device 2 to SNS_REPAIRING */
415  event.pe_index = 2;
416  target_state = M0_PNDS_SNS_REPAIRING;
417  event.pe_state = target_state;
418  rc = m0_poolmach_state_transit(pm, &event);
419  M0_UT_ASSERT(rc == 0);
420  /* the second spare slot is used by device 2 */
421  rc = m0_poolmach_sns_repair_spare_query(pm, 2, &spare_slot);
422  M0_UT_ASSERT(rc == 0);
423  M0_UT_ASSERT(spare_slot == 1);
424 
425 
426  /* transit device 1 to SNS_REPAIRED */
427  event.pe_index = 1;
428  target_state = M0_PNDS_SNS_REPAIRED;
429  event.pe_state = target_state;
430  rc = m0_poolmach_state_transit(pm, &event);
431  M0_UT_ASSERT(rc == 0);
432  /* the first spare slot is used by device 1 */
433  rc = m0_poolmach_sns_repair_spare_query(pm, 1, &spare_slot);
434  M0_UT_ASSERT(rc == 0);
435  M0_UT_ASSERT(spare_slot == 0);
436 
437  /* transit device 2 to SNS_REPAIRED */
438  event.pe_index = 2;
439  target_state = M0_PNDS_SNS_REPAIRED;
440  event.pe_state = target_state;
441  rc = m0_poolmach_state_transit(pm, &event);
442  M0_UT_ASSERT(rc == 0);
443  /* the second spare slot is used by device 2 */
444  rc = m0_poolmach_sns_repair_spare_query(pm, 2, &spare_slot);
445  M0_UT_ASSERT(rc == 0);
446  M0_UT_ASSERT(spare_slot == 1);
447 
448 
449  /* transit device 1 to SNS_REBALANCING */
450  event.pe_index = 1;
451  target_state = M0_PNDS_SNS_REBALANCING;
452  event.pe_state = target_state;
453  rc = m0_poolmach_state_transit(pm, &event);
454  M0_UT_ASSERT(rc == 0);
455  /* the first spare slot is used by device 1 */
456  rc = m0_poolmach_sns_rebalance_spare_query(pm, 1, &spare_slot);
457  M0_UT_ASSERT(rc == 0);
458  M0_UT_ASSERT(spare_slot == 0);
459 
460  /* transit device 2 to SNS_REBALANCING */
461  event.pe_index = 2;
462  target_state = M0_PNDS_SNS_REBALANCING;
463  event.pe_state = target_state;
464  rc = m0_poolmach_state_transit(pm, &event);
465  M0_UT_ASSERT(rc == 0);
466  /* the second spare slot is used by device 2 */
467  rc = m0_poolmach_sns_rebalance_spare_query(pm, 2, &spare_slot);
468  M0_UT_ASSERT(rc == 0);
469  M0_UT_ASSERT(spare_slot == 1);
470 
471 
472  /* transit device 2 to ONLINE */
473  event.pe_index = 2;
474  target_state = M0_PNDS_ONLINE;
475  event.pe_state = target_state;
476  rc = m0_poolmach_state_transit(pm, &event);
477  M0_UT_ASSERT(rc == 0);
478  rc = m0_poolmach_sns_repair_spare_query(pm, 2, &spare_slot);
479  M0_UT_ASSERT(rc == -ENOENT);
480 
481  /* transit device 3 to ONLINE */
482  event.pe_index = 3;
483  target_state = M0_PNDS_ONLINE;
484  event.pe_state = target_state;
485  rc = m0_poolmach_state_transit(pm, &event);
486  M0_UT_ASSERT(rc == 0);
487 
488  /* transit device 3 to FAILED */
489  event.pe_index = 3;
490  target_state = M0_PNDS_FAILED;
491  event.pe_state = target_state;
492  rc = m0_poolmach_state_transit(pm, &event);
493  M0_UT_ASSERT(rc == 0);
494  target_state = M0_PNDS_SNS_REPAIRING;
495  event.pe_state = target_state;
496  rc = m0_poolmach_state_transit(pm, &event);
497  M0_UT_ASSERT(rc == 0);
498  rc = m0_poolmach_sns_repair_spare_query(pm, 3, &spare_slot);
499  M0_UT_ASSERT(rc == 0);
500  M0_UT_ASSERT(spare_slot == 1);
501 
502  /* transit device 1 to ONLINE */
503  event.pe_index = 1;
504  target_state = M0_PNDS_ONLINE;
505  event.pe_state = target_state;
506  rc = m0_poolmach_state_transit(pm, &event);
507  M0_UT_ASSERT(rc == 0);
508  rc = m0_poolmach_sns_repair_spare_query(pm, 1, &spare_slot);
509  M0_UT_ASSERT(rc == -ENOENT);
510 
511  /* transit device 4 to ONLINE */
512  event.pe_index = 4;
513  target_state = M0_PNDS_ONLINE;
514  event.pe_state = target_state;
515  rc = m0_poolmach_state_transit(pm, &event);
516  M0_UT_ASSERT(rc == 0);
517 
518  /* transit device 4 to FAILED */
519  event.pe_index = 4;
520  target_state = M0_PNDS_FAILED;
521  event.pe_state = target_state;
522  rc = m0_poolmach_state_transit(pm, &event);
523  M0_UT_ASSERT(rc == 0);
524  target_state = M0_PNDS_SNS_REPAIRING;
525  event.pe_state = target_state;
526  rc = m0_poolmach_state_transit(pm, &event);
527  M0_UT_ASSERT(rc == 0);
528  rc = m0_poolmach_sns_repair_spare_query(pm, 4, &spare_slot);
529  M0_UT_ASSERT(rc == 0);
530  M0_UT_ASSERT(spare_slot == 0);
531 
532  /* We will keep the poolmach in persistent storage. It will be loaded
533  * in next test case.
534  */
535  /* finally */
536  pool_pver_fini();
537 }
538 
540  .ts_name = "poolmach-ut",
541  .ts_tests = {
542  { "pm_test init & fini", pm_test_init_fini },
543  { "pm_test state transit", pm_test_transit },
544  { "pm_test spare slot", pm_test_spare_slot },
545  { "pm_test multi fail", pm_test_multi_fail },
546  { NULL, NULL }
547  }
548 };
549 M0_EXPORTED(poolmach_ut);
550 #undef M0_TRACE_SUBSYSTEM
M0_INTERNAL void m0_pool_fini(struct m0_pool *pool)
Definition: pool.c:322
M0_INTERNAL int m0_poolmach_state_transit(struct m0_poolmach *pm, const struct m0_poolmach_event *event)
Definition: pool_machine.c:554
#define NULL
Definition: misc.h:38
struct m0_poolmach pv_mach
Definition: pool.h:133
static void pool_pver_fini(void)
Definition: test_pm.c:64
M0_INTERNAL int m0_poolmach_device_state(struct m0_poolmach *pm, uint32_t device_index, enum m0_pool_nd_state *state_out)
Definition: pool_machine.c:816
#define M0_SET0(obj)
Definition: misc.h:64
Definition: ut.h:77
#define N(i)
M0_INTERNAL int m0_pool_init(struct m0_pool *pool, const struct m0_fid *id, enum m0_pver_policy_code pver_policy)
Definition: pool.c:307
static struct m0_fid M0_POOL_ID
Definition: test_pm.c:45
#define M0_FID_TINIT(type, container, key)
Definition: fid.h:90
M0_INTERNAL void m0_fi_disable(const char *fp_func, const char *fp_tag)
Definition: finject.c:485
m0_pool_nd_state
Definition: pool_machine.h:57
static int pool_pver_init(uint32_t N, uint32_t K, uint32_t S)
Definition: test_pm.c:50
M0_INTERNAL void m0_poolmach_failvec_apply(struct m0_poolmach *pm, const struct m0_ha_nvec *nvec)
Definition: pool_machine.c:999
M0_INTERNAL int m0_pool_version_init(struct m0_pool_version *pv, const struct m0_fid *id, struct m0_pool *pool, uint32_t pool_width, uint32_t nr_nodes, uint32_t nr_data, uint32_t nr_failures, uint32_t nr_spare)
Definition: pool.c:522
static void pm_test_spare_slot(void)
Definition: test_pm.c:181
static struct m0_pool_version pver
Definition: test_pm.c:48
static struct m0_pool pool
Definition: test_pm.c:47
M0_INTERNAL void m0_pool_version_fini(struct m0_pool_version *pv)
Definition: pool.c:786
static void m0_fi_enable_off_n_on_m(const char *func, const char *tag, uint32_t n, uint32_t m)
Definition: finject.h:346
static void pm_test_transit(void)
Definition: test_pm.c:81
const char * ts_name
Definition: ut.h:99
static void pm_test_init_fini(void)
Definition: test_pm.c:71
Definition: fid.h:38
M0_INTERNAL int m0_poolmach_sns_repair_spare_query(struct m0_poolmach *pm, uint32_t device_index, uint32_t *spare_slot_out)
Definition: pool_machine.c:875
static void m0_fi_enable_once(const char *func, const char *tag)
Definition: finject.h:301
struct m0_ut_suite poolmach_ut
Definition: test_pm.c:539
Definition: rwlock.c:42
Definition: pool.h:80
static void pm_test_multi_fail(void)
Definition: test_pm.c:345
enum m0_pool_nd_state pe_state
Definition: pool_machine.h:199
static struct m0_fid M0_PVER_ID
Definition: test_pm.c:46
int32_t rc
Definition: trigger_fop.h:47
M0_INTERNAL int m0_poolmach_sns_rebalance_spare_query(struct m0_poolmach *pm, uint32_t device_index, uint32_t *spare_slot_out)
Definition: pool_machine.c:930
#define M0_UT_ASSERT(a)
Definition: ut.h:46